1. Field of the Invention
The present invention relates to a memory device with an output buffer. More specifically, the present invention discloses an output buffer with an output signal that is generated from a sense amplifier.
2. Description of the Prior Art
Please refer to FIG. 1 and FIG. 2. FIG. 1 is a diagram of a memory circuit 10 according to the prior art. FIG. 2 is a diagram of a memory array 12 as shown in FIG. 1. The memory circuit 10 comprises a memory array 12, an address buffer 14, a row decoder 16, a column decoder 18, a sense amplifier 22, and an output buffer 28. The memory array 12 comprises a plurality of word lines 32, a plurality of bit lines 34 and a plurality of memory cells 36. Each of the memory cells 36 is coupled to a corresponding word line 32 and a corresponding bit line 34, and is used for storing one binary bit of data.
When data stored in one of the memory cells 36 is to be accessed, a corresponding address signal ADRS is transmitted to the memory circuit 10, and the memory circuit 10 then outputs a corresponding data output signal Dout. The address buffer 14 transforms the address signal ADRS, transmitted from an input terminal of the memory circuit 10, into two address signals AX and AY. The address signals AX and AY are then sent to the row decoder 16 and the column decoder 18, respectively. The row decoder 16 selects a corresponding word line 32 according to the address signal AX, and the column decoder 18 selects a corresponding bit line 34 according to the address signal AY. In this manner, the memory cell 36 corresponding to the address signal ADRS outputs a corresponding data signal to the sense amplifier 22 according to the data stored within this cell 36. The sense amplifier 22 amplifies the data signal outputted from the memory cell 36 to determine if the data stored in the memory cell 36 is a binary xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d, and thereby generates an output signal SA/SAB. The output signal SA/SAB comprises two complementary voltage signals SA and SAB. When the voltage signal SA is a high voltage, the voltage signal SAB is a low voltage, and vice versa, when the voltage signal SA is a low voltage, then the voltage signal SAB is a high voltage. The output signal SA/SAB is transmitted from a data output port 38 of the sense amplifier 22 to the output buffer 28, which has a control terminal 42 for accepting a control signal OE. When the control signal OE is high, the output buffer 28 amplifies the output signal SA/SAB to generate the data output signal Dout, and when the control signal OE is low, the output buffer 28 does not amplify the output signal SA/SAB.
While the represented data of the output signal SA/SAB is in an undefined state, the memory circuit 10 utilizes an address transition detector (ATD) 24 and a delay circuit 26 for producing the control signal OE so as to control the output of the output buffer, thus preventing an undefined output signal SA/SAB from being amplified by the output buffer 28, which could otherwise adversely affect the accuracy of the data output signal Dout. The address transition detector 24 is used to detect variations of the address signals AX and AY to generate a control signal ADT. The delay circuit 26 is used to delay the control signal ADT for a predetermined time interval, and the signal outputted from the delay circuit 26 is the control signal OE.
Please refer to FIG. 3, which is a timing diagram of signals generated in the memory circuit 10. The output signal SA/SAB is represented, respectively, by two complementary voltage signals SA and SAB. Data outputted from the memory cell 36 is a xe2x80x9c1xe2x80x9d when the voltage signal SA is greater than a first predetermined high voltage VH1 and the voltage signal SAB is smaller than a first predetermined low voltage VL1 (an interval T2 as shown in FIG. 3). The data outputted from the memory cell 36 is a xe2x80x9c0xe2x80x9d when the voltage signal SA is smaller than the first predetermined low voltage VL1 and the voltage signal SAB is greater than the first predetermined high voltage VH1 (an interval T4 as shown in FIG. 3). The data outputted from the memory cell 36 is undefined when any one of the voltage signals SA or SAB is between the first predetermined high voltage VH1 and the first predetermined low voltage VL1 (intervals T1 and T3 as shown in FIG. 3).
As shown in FIG. 3, when the control signal OE rises from a second predetermined low voltage VL2 to a second predetermined high voltage VH2, the output buffer 28 amplifies the output signal SA/SAB and generates the data output signal Dout. When the control signal OE drops from the second predetermined high voltage VH2 to the second predetermined low voltage VL2, the output buffer 28 stops amplifying the output signal SA/SAB. The amplitude of the data output signal Dout varies between a third predetermined high voltage VH3 and a third predetermined low voltage VL3, and the outputted data of the memory circuit 10 is a xe2x80x9c1xe2x80x9d or a xe2x80x9c0xe2x80x9d according to the amplitude of the output signal Dout, which is output from the output buffer 28. When the amplitude of the output signal Dout equals the third predetermined high voltage VH3, the outputted data is a xe2x80x9c1xe2x80x9d. When the amplitude of the output signal Dout equals the third predetermined low voltage VL3, the outputted data is a xe2x80x9c0xe2x80x9d. When the control signal OE drops from the second predetermined high voltage VH2 to the second predetermined low voltage VL2, i.e., when the output buffer 28 stops amplifying the output signal SA/SAB, the amplitude of the output signal Dout will be a middle voltage VM regardless of whether the amplitude of the output signal Dout should be equal to the predetermined third high voltage VH3 or the predetermined third low voltage VL3. The middle voltage VM is approximately equal to the average of VH3 and VL3, i.e, VM (VH3+VL3)/2.
Although the desired time interval of the delayed control signal ATD from the delay circuit 26 is determined before manufacturing the memory circuit 10, the actual delay time interval of the delay circuit 26 varies with an operating temperature of the memory circuit 10, or due to manufacturing processes of the memory circuit 10. When the variation of the delayed time interval exceeds a predetermined range, the speed and accuracy of the memory circuit 10 will be affected. If the delayed time interval of the delay circuit 26 is longer, the accessing speed of the memory circuit 10 is reduced. As shown in FIG. 3, when the represented data of the output signal SA/SAB has confirmed and past a predetermined time interval Tout, the control signal OE rises to the second predetermined high voltage VH2, and the output buffer 28 begins amplifying the output signal SA/SAB. When the delayed time interval of the delay circuit 26 is longer, the predetermined time interval Tout is also longer, so the accessing time interval of the memory circuit 10 is longer, which causes the accessing speed to become slower. On the other hand, when the delayed time interval of the delay circuit 26 is shorter, the accessing speed of the memory circuit 10 becomes faster. However, the memory circuit 10 will more easily generate errors during the data accessing process if the delayed time interval of the delay circuit 26 is too short.
Please refer to FIG. 4, which is a timing diagram of signals generated in the memory circuit 10 when a data accessing error occurs. As shown in FIG. 4, when the presented data of the output signal SA/SAB is undefined, that is, when any one of the voltage signals SA or SAB is between the first predetermined high voltage VH1 and the first predetermined low voltage VL1, the control signal OE rises from the second predetermined low voltage VL2 to the second predetermined high voltage VH2. In the data translation process of the output signal SA/SAB from a xe2x80x9c0xe2x80x9d to a xe2x80x9c1xe2x80x9d (an interval T5 as shown in FIG. 4), at a time point Ta, the data of the output signal SA/SAB are interpreted as a xe2x80x9c0xe2x80x9d, so that the data output signal Dout drops from the middle voltage VM. At the time point Tb, the data of the output signal SA/SAB are interpreted as a xe2x80x9c1xe2x80x9d, so that the data output signal Dout rises to the third predetermined high voltage VH3. On the other hand, in the translation process of the data of the output signal SA/SAB from a xe2x80x9c1xe2x80x9d to a xe2x80x9c0xe2x80x9d (an interval T6 as shown in FIG. 4), at a time point Tc, the data of the output signal SA/SAB are interpreted as a xe2x80x9c1xe2x80x9d, so that the data output signal Dout rises from the middle voltage VM. At a time point Td, the data of the output signal SA/SAB are interpreted as a xe2x80x9c0xe2x80x9d, so that the data output signal Dout drops to the third predetermined low voltage VL3. As mentioned above, when the presented data of the data output signal Dout is undefined, if the output buffer 28 begins amplifying the output signal SA/SAB, the data output signal SA/SAB generated from the output buffer 28 will produce the above-mentioned phenomena that adversely affects the accuracy of the data when accessing the memory circuit 10.
It is therefore a primary objective of the present invention to provide a memory circuit with an output buffer for controlling control signals of the output buffer so as to improve an accessing speed of the memory circuit, according to output signals generated from a sense amplifier.
The present invention discloses a memory device having an output buffer. The output buffer is electrically connected to a data output port of a sense amplifier of the memory device for amplifying an output signal from the data output port. The output buffer has a detector for producing a control signal according to the output signal from the data output port, and an amplifier for amplifying the output signal from the data output port. The amplifier has an input port electrically connected to the data output port for accepting the output signal from the data output port, and a control terminal electrically connected to the output terminal of the detector for accepting the control signal from the detector to control operations of the amplifier. When the detector produces the control signal and transmits the control signal to the control terminal of the amplifier, the amplifier begins amplifying the output signal transmitted from the data output port to the input port of the amplifier.
It is an advantage of the present invention that the memory circuit having an output buffer generates the control signal for controlling operations of the output buffer according to the amplitude of the output signal outputted from the sense amplifier, so when data of the output signal outputted from the sense amplifier are defined, the output buffer begins operating, and the accessing speed of the memory circuit is increased.
These and other objectives and advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.